1. Field of the Invention
The present invention relates to a power control apparatus for a computer system which may adaptively apply to office automation equipment.
2. Description of the Related Art
The inventors of the present application know a representative computer system which is arranged as follows. This computer system is arranged to have a microprocessor (such as CPU), a data cache memory, an instruction cache memory, a bus interface, a random access memory (RAM), a read-only memory (ROM) and various I/O units.
The microprocessor, the bus interface, the data cache memory and the instruction cache memory may be integrated on one chip or more than one chips.
The above mentioned computer system is actually implemented in some computers such as R3000 manufactured by the MIPS Computer Systems, INC. in USA (for example, see "MIPS SET Technical Manual" published by the LSI Logic Inc., Order No. 63004, Part No. MM71-000101-99A).
The microprocessor (CPU) designed by the MIPS Computer Systems is grouped as a RISC (Reduced Instruction Set Computer). This computer achieves a fast processing speed, because it can access the instruction or data at one machine cycle if it is stored in a cache memory. Normally, the CPU checks if the instruction or data is stored in the cache memory at each machine cycle with the cache bus and continues to access the cache memory for processing if it is stored therein.
Next, consider the flow of pipelines in the microprocessor R3000 having five pipeline stages.
The microprocessor R3000 includes five pipelines which are executed in a manner to overlap one pipeline with the adjacent pipeline. As such, if the instruction or data exists in the cache memory, one instruction can be processed at one clock cycle. The five pipelines are a Fetch (IF) stage for fetching an instruction from the cache memory, a register decode (RD) stage, an arithmetic logic unit (ALU) stage, a memory access (MEM) stage, a write back (WB) stage for writing back the data to the register, respectively.
Then, the description will be oriented to a way of which the microprocessor R3000 operates if no hit takes place in the instruction cache.
The instruction to be executed by the microprocessor (CPU) is located in the RAM for the first time. The CPU serves to read out the instruction from the cache memory for executing an instruction. Since the instruction is located in the RAM, a miss hit takes place in the cache memory.
Next, the CPU enters into a stall cycle for reading the instruction from the RAM through the bus interface. Then, the CPU accesses the RAM through the bus interface and writes the read instruction in the cache memory (at a fix-up cycle). The CPU fetches the instruction from the cache memory and starts to run again.
In general, the microprocessor (CPU) provides a highly localized program, that is, although the instruction is read by the cache memory once, it may be very frequently used again. If the instruction exists (referred to "is hit") in the cache memory, the operation flows smoothly through the five pipelines so that the microprocessor can read the instruction and continues to run at one access cycle by an effective one instruction. Hence, the microprocessor makes use of the following relation when it is in operation. EQU Access Time for RAM&gt;Access Cycle Time for Cache Memory
The foregoing description holds true to an operation of accessing the cache for data. Further, the foregoing description has concerned with accessing the RAM if a miss hit on the cache takes place. In place, consider that the microprocessor accesses the I/O unit or the ROM connected on the system bus. For accessing these units, the microprocessor uses a logic address space without using the cache memory. As such, like the case of the miss hit on the cache memory, the stall cycle is needed.
If no hit on the cache memory takes place (a "miss hit") at the MEM stage, another stall cycle for accessing the RAM takes place so that the MEM stage of the next instruction will be set in the waiting state.
From a quantitative point of view, assuming that the access to the RAM consumes N-1 cycles, the instruction is written in the cache memory before the microprocessor restarts to run, and let the probability of hitting the cache memory to be A %, then the number of average cycles required for executing one instruction is given by the following relation: EQU 1.times.A/100+N.times.(1-A/100)
For example, if A=98% and N=4 cycles, this formula can be calculated as: EQU 1.times.98/100+4.times.(1-98/100)=1.06
In this case, the number of average cycles needed for executing an instruction comes closer to 1. The effective processing speed of the CPU comes closer to the clock cycle of the CPU. It means that the processing speed is substantially maintained.
This is the principle in which the computer system provided with a cache memory operates.
This principle holds true to accessing the cache for reading data, that is, the computer system executes to read an instruction from the cache memory and to read or write data as frequently as the machine cycle on which the computer system depends.
If the current execution process stays in the waiting state for an I/O and no execution process is left in the computer system, this state is referred to as an idle state in which the computer system is controlled to execute an idle loop or execute a stop instruction so that the interrupt of the I/O unit may get the computer system itself out of the idle state.
The inventors of the present applicant know the following method of causing an idle state.
As the simplest idle state, (1) the idle loop is executed until the interrupt from the I/O unit takes place. In this method, no significant process is executed in the idle state. However, such an idle state often takes place when waiting for an interrupt from the I/O unit. Hence, to conserve the power consumption in this state, some methods have been considered.
For example, in the CPU of MC68000 manufactured by Motorola Inc., a stop instruction for stopping an operation of the CPU is prepared in the instruction set. This stop instruction is used, that is, (2) the instruction for stopping the CPU in the idle state is executed for putting the CPU into the stopping state and then the CPU enters into the state of waiting for an interrupt from an I/O unit.
If an interrupt from an I/O unit takes place, the CPU returns from the stopping state.
If the microprocessor is manufactured by CMOS (Complementary Metal Oxide Silicon), it may use a proportional relation between power consumption and clock frequency for lowering the clock frequency.
If the microprocessor is a RISC CPU such as SPARC CPU CY7C601 manufactured by CYPRESS Company, it makes use of the fact that nothing unfavorable takes place if the CPU clock is stopped, that is, (3) to cause an idle state, the microprocessor accesses the I/O unit for stopping the CPU clock and if an interrupt from an I/O unit takes place, the CPU clock is restarted.
Such a function needs another circuit for controlling a CPU clock in addition to the CPU. Further, as a transformation of the method (3), the clock frequency may be lowered without making the CPU clock zero. Since the CPU or the cache memory manufactured in the recent CMOS process increases a power consumption proportional to the operating frequency, the method (3) including its transformation makes it possible to lower the power consumption.
As a combination of these methods, in the Japanese Patent Application Lying Open No. 3-14111, "Power-saving Control Unit for Microprocessor", a method for both issuing a CPU-stopping instruction and stopping a CPU clock at the same time, is disclosed.
In the above mentioned method (1), the overall idling loop is loaded in each cache memory, because the number of instructions for an idling loop is small. As a result, the idling loop is executed at a speed of one instruction/one clock. The operation of the CPU/Cache memory fully depends on the operating speed of the CPU clock. Hence, the power consumption of the computer system is mainly for the CPU and the cache memory, and this leads to disability to reduce the power consumption for idling.
The above mentioned method (2) has a shortcoming that it cannot be adapted to the CPU providing no CPU-stopping instruction. In actual, the commercially available CPUs normally provide such an instruction, hence this method has a low feasibility.
The above mentioned method (3) has a shortcoming that if the CPU does not employ a static design, the CPU clock is not made zero or lowered. In actual, the commercially available CPUs normally do not provide such a static design. Further, in the most of the CPUs, the CPU clock is equal to the system bus clock or a multiple of the system bus clock. In such systems, the CPU clock is disallowed to be changed.